Liquid crystal display and thin film transistor array panel therefor

ABSTRACT

A thin film transistor array panel is provided, which includes: a gate line and a data line formed on an insulating substrate and intersecting each other; a plurality of common electrodes separated from the gate line and the data line and making an angle of about 7-23 degrees with the gate line; a plurality of pixel electrodes separated from the gate line, the data line, and the common electrodes, extending parallel to the common electrodes, and alternately arranged with the common electrodes; and a thin film transistor connected to the gate line, the data line, and the pixel electrodes.

BACKGROUND OF THE INVENTION

(a) Field of the Invention

The present invention relates to a liquid crystal display and a thinfilm transistor array panel.

(b) Description of the Related Art

A liquid crystal display (LCD) is one of the most widely used flat paneldisplays. An LCD includes two panels provided with field-generatingelectrodes and a liquid crystal (LC) layer interposed therebetween. TheLCD displays images by applying voltages to the field-generatingelectrodes to generate an electric field in the LC layer, whichdetermines orientations of LC molecules in the LC layer to adjustpolarization of incident light.

Among LCDs including field-generating electrodes on respective panels, akind of LCDs called in-plane switching (IPS) mode LCD provides aplurality of pixel electrodes and a plurality of common electrode at onepanel. The pixel electrodes and the common electrodes are alternatelyarranged and generate an electric field substantially parallel tosurface of the panels. The IPS LCD is known to have superior viewingangle to a twisted-nematic (TN) mode LCD.

The image display of the LCD is accomplished by applying individualvoltages to the respective pixel electrodes. For the application of theindividual voltages, a plurality of three-terminal thin film transistors(TFTs) are connected to the respective pixel electrodes, and a pluralityof gate lines transmitting signals for controlling the TFTs and aplurality of data lines transmitting voltages to be applied to the pixelelectrodes are provided on the panel.

Since the IPS mode LCD has disadvantages of lateral color shifts andgray inversion in a direction, LCDs having curved pixel electrodes andcurved common electrodes as shown in FIGS. 10A and 10B are suggested.However, the LCD shown in FIG. 10A has a disadvantage of increasedresistance and parasitic capacitance of data lines, and the LCD shown inFIG. 10B has a disadvantage of reduced aperture ratio due to increasedcommon electrodes.

SUMMARY OF THE INVENTION

A motivation of the present invention is to solve the problems of theconventional art.

A thin film transistor array panel is provided, which includes: a gateline and a data line formed on an insulating substrate and intersectingeach other; a plurality of common electrodes separated from the gateline and the data line and making an angle of about 7-23 degrees withthe gate line; a plurality of pixel electrodes separated from the gateline, the data line, and the common electrodes, extending parallel tothe common electrodes, and alternately arranged with the commonelectrodes; and a thin film transistor connected to the gate line, thedata line, and the pixel electrodes.

The common electrodes preferably include first and second electrodesmaking an angle of about 15-45 degrees.

The thin film transistor array panel may further include a connectingelectrode connecting the common electrodes and a common electrode lineextending parallel to the gate line and connected to the connectingelectrode.

The thin film transistor array panel may further include a pixelelectrode line connecting the pixel electrodes and extending parallel tothe data lines.

A thin film transistor array panel is provided, which includes: aninsulating substrate; a gate line formed on the insulating substrate; acommon electrode line including a plurality of branched commonelectrodes making an angle of about 7-23 degrees with the gate line; agate insulating layer on the gate line; a semiconductor layer on thegate insulating layer; a data line formed at least in part on thesemiconductor layer; a pixel electrode line formed at least in part onthe semiconductor layer and including a plurality of branched pixelelectrodes alternately arranged with the common electrodes; and apassivation layer formed on the data line and the pixel electrode line.

The common electrodes preferably include first and second electrodesmaking an angle of about 15-45 degrees with each other.

The pixel electrodes preferably include third and fourth electrodesextending parallel to the first and the second electrodes, respectively.

The thin film transistor array panel may further include a redundantsignal line formed on the passivation layer and extending along the dataline, and the passivation layer preferably has a contact hole forconnection between the data line and the redundant signal line.

The thin film transistor array panel may further include a contactassistant formed on the passivation layer, and the passivation layerpreferably has a contact hole exposing a portion of the data line andcovered by the contact assistant.

Preferably, the common electrode line extends substantially parallel tothe gate line and further includes a frame connecting the commonelectrodes.

The pixel electrode line preferably extends substantially parallel tothe data line.

The thin film transistor array panel may further include an ohmiccontact disposed between the semiconductor layer and the data line andthe pixel electrode line.

The semiconductor layer may have substantially the same planar shape asthe data line and the pixel electrode line and the ohmic contact.

A liquid crystal display is provided, which includes: a first substrate;a gate line and a data line formed on the first substrate andintersecting each other; a plurality of common electrodes separated fromthe gate line and the data line and making an angle of about 7-23degrees with the gate line; a plurality of pixel electrodes separatedfrom the gate line, the data line, and the common electrodes, extendingparallel to the common electrodes, and alternately arranged with thecommon electrodes; a thin film transistor connected to the gate line,the data line, and the pixel electrodes; a second substrate; and aliquid crystal layer interposed between the first substrate and thesecond substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other advantages of the present invention will become moreapparent by describing preferred embodiments thereof in detail withreference to the accompanying drawings in which:

FIG. 1 is a layout view of an exemplary TFT array panel for an LCDaccording to an embodiment of the present invention;

FIG. 2 is a sectional view of the TFT array panel shown in FIG. 1 takenalong the line II-II′;

FIG. 3 is a layout view of an exemplary TFT array panel for an LCDaccording to another embodiment of the present invention;

FIG. 4 is a sectional view of the TFT array panel shown in FIG. 3 takenalong the lines IV-VI′, IV′-IV″and IV″-IV″′;

FIGS. 5-9 are sectional views of a TFT array panel shown in FIGS. 3 and4 in intermediate steps of a manufacturing method thereof according toan embodiment of the present invention; and

FIGS. 10A and 10B are layout views of TFT array panels for conventionalLCDs.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

The present invention now will be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. The present invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein.

In the drawings, the thickness of layers, films and regions areexaggerated for clarity. Like numerals refer to like elementsthroughout. It will be understood that when an element such as a layer,film, region or substrate is referred to as being “on” another element,it can be directly on the other element or intervening elements may alsobe present. In contrast, when an element is referred to as being“directly on” another element, there are no intervening elementspresent.

Now, liquid crystal displays, TFT array panels for LCDs, andmanufacturing methods thereof according to embodiments of the presentinvention will be described with reference to the accompanying drawings.

FIG. 1 is a layout view of an exemplary TFT array panel for an LCDaccording to an embodiment of the present invention, and FIG. 2 is asectional view of the TFT array panel shown in FIG. 1 taken along theline II-II′.

A plurality of gate lines 121 for transmitting gate signals and aplurality of common electrode lines 131 for transmitting a commonvoltage are formed on an insulating substrate 110.

Each gate line 121 extends substantially in a transverse direction and aplurality of portions of each gate line 121 form a plurality of gateelectrodes 123.

Each common electrode line 131 extends substantially in the transversedirection and includes a plurality of sets of branches, and each set ofbranches include a frame 132 and a plurality of common electrodes 133 aand 133 b connected to the frame 132. The frame 132 has a rectangularshape including four edges. The common electrodes 133 a and 133 bobliquely extend and the common electrodes 133 a extend from a left edgeof the frame 132 in an upper right direction while the common electrodes133 b extend from the left edge of the frame 132 in a lower rightdirection. The extensions of the common electrodes 133 a and 133 b meetthe gate lines 121 at an angle of about 15±8 degrees, i.e., in a rangeof about 7 to 23 degrees and thus they meet each other at an angle in arange of about 14 to 46 degrees, preferably in a range of about 15 to 45degrees.

The gate lines 121 and the common electrode lines 131 may include twofilms having different physical characteristics, a lower film (notshown) and an upper film (not shown). The upper film is preferably madeof low resistivity metal including Al containing metal such as Al and Alalloy for reducing signal delay or voltage drop in the gate lines 121and the common electrode lines 131. On the other hand, the lower film ispreferably made of material such as Cr, Mo and Mo alloy, which has goodcontact characteristics with other materials such as indium tin oxide(ITO) or indium zinc oxide (IZO). A good exemplary combination of thelower film material and the upper film material is Cr and Al-Nd alloy.

In addition, the lateral sides of the gate lines 121 and the commonelectrode lines 131 are tapered, and the inclination angle of thelateral sides with respect to a surface of the substrate 110 rangesabout 30-80 degrees.

A gate insulating layer 140 preferably made of silicon nitride (SiNx) isformed on the gate lines 121 and the common electrode lines 131.

A plurality of semiconductor stripes 151 preferably made of hydrogenatedamorphous silicon (abbreviated to “a-Si”) or polysilicon are formed onthe gate insulating layer 140. Each semiconductor stripe 151 extendssubstantially in a longitudinal direction and has a plurality ofprojections 154 branched out toward the gate electrodes 123.

A plurality of ohmic contact stripes and islands 161 and 165 preferablymade of silicide or n+hydrogenated a-Si heavily doped with n typeimpurity are formed on the semiconductor stripes 151. Each ohmic contactstripe 161 has a plurality of projections 163, and the projections 163and the ohmic contact islands 165 are located in pairs on theprojections 154 of the semiconductor stripes 151.

The lateral sides of the semiconductor stripes 151 and the ohmiccontacts 161 and 165 are tapered, and the inclination angles thereof arepreferably in a range between about 30-80 degrees.

A plurality of data lines 171 and a plurality of pixel electrode lines172 separated from each other are formed on the ohmic contacts 161 and165 and the gate insulating layer 140.

The data lines 171 for transmitting data voltages extend substantiallyin the longitudinal direction and intersect the gate lines 121 and thecommon electrode lines 131. Each pixel electrode lines 172 extendsubstantially in the longitudinal direction and includes a plurality ofbranches 174 a-174 c called pixel electrodes. The pixel electrodes 174 aand 174 b extend parallel to the common electrodes 133 a and 133 brespectively, and the pixel electrode 174 c extends along the commonelectrode line 131 and is bifurcated into two branches parallel to thecommon electrodes 133 a and 133 b, respectively.

Each data line 171 includes a plurality of branches of each data line171 projecting toward the gate lines 123 to form a plurality of sourceelectrodes 173, and each pixel electrode line 172 further includes anextension 175 projecting toward the source electrode 173 forming a drainelectrode 175. Each pair of the source electrodes 173 and the drainelectrodes 175 are opposite each other with respect to a gate electrode123. A gate electrode 123, a source electrode 173, and a drain electrode175 along with a projection 154 of a semiconductor stripe 151 form a TFThaving a channel formed in the projection 154 disposed between thesource electrode 173 and the drain electrode 175.

The pixel electrodes 174 a-174 c receive the data voltages from thedrain electrodes 175 and generate electric fields in cooperation withthe common electrodes 133 a and 133 b, which reorient liquid crystalmolecules in the liquid crystal layer disposed therebetween. The pixelelectrodes 174 a-174 c and the common electrodes 133 a and 133 b form aliquid crystal capacitor, which stores applied voltages after turn-offof the TFT. An additional capacitor called a “storage capacitor,” whichis connected in parallel to the liquid crystal capacitor, is providedfor enhancing the voltage storing capacity. The storage capacitors areimplemented by overlapping the pixel electrode lines 172 with the frames132 of the common electrode lines 131.

The data lines 171 and the pixel electrode lines 172 may also include alower film (not shown) preferably made of Mo, Mo alloy or Cr and anupper film (not shown) located thereon and preferably made of Alcontaining metal.

Like the gate lines 121 and the common electrode lines 131, the datalines 171 and the pixel electrode lines 172 have tapered lateral sides,and the inclination angles thereof range about 30-80 degrees.

The ohmic contacts 161 and 165 are interposed only between theunderlying semiconductor stripes 151 and the overlying data lines 171and the overlying drain electrodes 175 thereon and reduce the contactresistance therebetween. The semiconductor stripes 151 include aplurality of exposed portions, which are not covered with the data lines171 and the drain electrodes 175, such as portions located between thesource electrodes 173 and the drain electrodes 175. Although thesemiconductor stripes 151 are narrower than the data lines 171 at mostplaces, the width of the semiconductor stripes 151 becomes large nearthe gate lines 121 as described above, to enhance the insulation betweenthe gate lines 121 and the data lines 171.

A passivation layer 180 is formed on the data lines 171 and the pixelelectrode lines 172, and the exposed portions of the semiconductorstripes 151. The passivation layer 180 is preferably made ofphotosensitive organic material having a good flatness characteristic,low dielectric insulating material such as a-Si:C:O and a-Si:O:F formedby plasma enhanced chemical vapor deposition (PECVD), or inorganicmaterial such as silicon nitride.

The passivation layer 180 has a plurality of contact holes 182 and 183exposing end portions 179 of the data lines 171 and mid-portions of thedata lines 171, respectively. The passivation layer 180 and the gateinsulating layer 140 have a plurality of contact holes 181 exposing endportions 125 of the gate lines 121. The contact holes 181-183 can havevarious shapes such as polygon or circle. The area of each contact hole181 or 182 is preferably equal to or larger than 0.5 mm×15 μm and notlarger than 2 mm×60 μm.

A plurality of redundant data lines 191 and a plurality of contactassistants 95 and 97, which are preferably made of ITO, IZO or Cr, areformed on the passivation layer 180.

The redundant data lines 191 are connected to the data lines 171 throughthe contact holes 183 to form compensatory signal paths of the datavoltages. The contact assistants 95 and 97 are connected to the exposedend portions 125 of the gate lines 121 and the exposed end portions 179of the data lines 171 through the contact holes 181 and 182,respectively. The contact assistants 95 and 97 are not requisites butpreferred to protect the exposed portions 125 and 179 and to complementthe adhesiveness of the exposed portion 125 and 179 and externaldevices.

Finally, an alignment layer 11 is formed on the redundant data lines191, the contact assistants 95 and 97, and the passivation layer 180.The alignment layer 11 is rubbed in a direction indicated by an arrow asshown in FIG. 1, which is substantially parallel to the gate lines 121.

An LCD according to an embodiment includes the TFT array panel shown inFIGS. 1 and 2, a color filter array panel (not shown) provided with aplurality of color filters and an alignment layer coated on the colorfilters and rubbed in the direction indicated by the arrow shown in FIG.1, and a liquid crystal layer (not shown) interposed therebetween.Liquid crystal molecules in the liquid crystal layer are aligned suchthat their long axes are parallel to surfaces of the panels and therubbing direction. The liquid crystal layer has a positive dielectricanisotropy.

Upon application of the common voltage and the data voltage to thecommon electrodes 133 a and 133 b and the pixel electrodes 174 a-174 c,an electric field substantially parallel to the surfaces of the panelsand substantially perpendicular to the extension direction of the commonelectrodes 133 a and 133 b and the pixel electrodes 174 a-174 c isgenerated. The liquid crystal molecules tend to change theirorientations in response to the electric field such that their long axesare parallel to the field direction.

An LCD including the TFT array panel shown in FIGS. 1 and 2 is comparedwith conventional LCDs shown in FIGS. 10A and 10B, which are layoutviews of conventions LCDs. conventional LCD 1 meeting angle about 150°about 150° about 30° between electrodes 2 rubbing direction parallel toparallel to parallel to gate line data line data line (advantageous forpreventing lateral crosstalk) 3 shape of pixel area zigzag rectanglerectangle (advantageous for reducing signal delay in data line) 4 numberof 3 or 5 3 or 5 1 disclination lines (advantageous for increasingluminance) 5 decrease of none some none aperture ratio due (advantageousfor to common improving aperture electrode ratio) 6 facility of varyingdifficult difficult easy distance between electrodes

The initial orientations of the liquid crystal molecules shown in FIG. 1are parallel to the gate lines, i.e., perpendicular to the data lines,while those shown in FIGS. 10A and 10B are parallel to the data lines.Meanwhile, the voltage difference between the data lines and the pixelelectrode lines form electric fields perpendicular to the data lines,which interfere electric fields between the common electrodes and thepixel electrodes shown in FIGS. 10A and 10B, thereby causing lateralcrosstalk. However, since the electric field between the data lines andthe pixel electrode lines has the same field direction as the electricfield between the common electrodes and the pixel electrodes in the LCDshown in FIGS. 1 and 2, there is no lateral crosstalk.

The rectangular shape of pixel areas allows rectilinear data lines,which have smaller resistance and parasitic capacitances than the datalines shown in FIG. 10A. Therefore, the rectangular shape of the pixelareas is advantageous for reducing the signal delay in the data lines.

The disclination lines are generated near the areas where theorientations of the liquid crystal molecules vary. The molecularorientations shown in FIG. 1 vary only near the pixel electrode 74 c,while those shown in FIGS. 10A and 10B vary near the three curves of thepixel electrodes. Accordingly, the number of the disclination linesshown in FIG. 1 is very small compared with those shown in FIGS. 10A and10B.

The LCD shown in FIG. 10B includes a pair of wide common electrodes nearthe data lines for making rectangular pixel areas, which reduces theaperture ratio. However, there is no such problem in the LCD shown inFIGS. 1 and 2.

The pixel electrodes and the common electrodes shown in FIGS. 10A and10B extend parallel to the data lines rather than the gate lines, whilethose shown in FIGS. 1 and 2 extend parallel to the gate lines ratherthan the data lines. Since the distance between the gate lines is muchlarger than the distance between the data lines, the variation of thenumber of the electrodes and the distance between the electrodes in theLCD shown in FIG. 1 is very easy compared with that shown in FIGS. 10Aand 10B.

A method of manufacturing the TFT array panel shown in FIGS. 1 and 2according to an embodiment of the present invention will be nowdescribed in detail.

A plurality of gate lines 121 including a plurality of gate electrodes123 and a plurality of common electrode lines 131 including a pluralityof common electrodes 133 a and 133 b are formed on an insulatingsubstrate 110 such as transparent glass.

When the gate lines 121 and the common electrode lines 131 have adouble-layered structure including a lower conductive film and an upperconductive film, the lower conductive film is preferably made ofmaterial such as Mo or Cr alloy having good physical and chemicalcharacteristics and the upper conductive film is preferably made of Alor Al containing metal.

The lower film of Mo alloy and the upper film of Ag alloy can besimultaneously patterned by wet etching preferably using an Ag etchantcontaining phosphoric acid, nitric acid, acetic acid, and pure water.Since the etching ratio for Ag alloy is larger than that for Mo alloy, ataper angle of about 30 degrees can be obtained.

After sequential deposition of a gate insulating layer 140, an intrinsica-Si layer, and an extrinsic a-Si layer, the extrinsic a-Si layer andthe intrinsic a-Si layer are photo-etched to form a plurality ofextrinsic semiconductor stripes 164 and a plurality of intrinsicsemiconductor stripes 151 including a plurality of projections 154 onthe gate insulating layer 140.

Subsequently, a plurality of date lines 171 including a plurality ofSource electrodes 173 and a plurality of pixel electrode lines 172including a plurality of drain electrodes 175 and a plurality of pixelelectrodes 74 a-74 c are formed.

Thereafter, portions of the extrinsic semiconductor stripes 164, whichare not covered with the data lines 171 and the pixel electrode lines172, are removed to complete a plurality of ohmic contact stripes 161including a plurality of projections 163 and a plurality of ohmiccontact islands 165 and to expose portions of the intrinsicsemiconductor stripes 151. Oxygen plasma treatment preferably followsthereafter in order to stabilize the exposed surfaces of thesemiconductor stripes 151.

A passivation layer 180 is formed by growing a-Si:C:O or a-Si:O:F, byCVD of inorganic material such as silicon nitride, or by coating anorganic insulating material such as acryl-based material. When formingan a-Si:C:O layer, SiH(CH₃)₃, SiO₂(CH₃)₄, (SiH)₄O₄(CH₃)₄, Si(C₂H₅O)₄ orthe like used as basic source, oxidant such as N₂O or O₂, and Ar or Heare mixed in gaseous states to flow for the deposition. For an s-Si:O:Flayer, the deposition is performed by flowing a gas mixture includingSiH₄, SiF₄ or the like and an additional gas of O₂. CF₄ may be added asa secondary source of fluorine.

After depositing a passivation layer 180, the passivation layer 180 andthe gate insulating layer 140 are patterned to form a plurality ofcontact holes 181, 182 and 183 exposing end portions 125 of the gatelines 121, end portions 179 of the data lines 171, and mid-portions ofthe data lines 171, respectively.

Finally, a plurality of redundant data lines 191 and a plurality ofcontact assistants 95 and 97 are formed on the passivation layer 180 bysputtering and photo-etching IZO, ITO or Cr layer.

An example of sputtering target for the IZO layer is IDIXO (indiumx-metal oxide) produced by Idemitsu Co. of Japan. The sputtering targetincludes In₂O₃ and ZnO, and the ratio of Zn with respect to the sum ofZn and In is preferably in a range of about 15-20 atomic %. Thepreferred sputtering temperature for minimizing the contact resistanceis equal to or lower than about 250° C. The etching of the IZO or ITOlayer preferably includes wet etching using a Cr etchant ofHNO₃/(NH₄)₂Ce(NO₃)₆/H₂O, which does not erode Al of the data lines 171,the drain electrodes 175, the gate lines 121, the storage electrodelines 131, and the storage electrodes 133 a-133 e. Nitrogen gas, whichprevents the formation of metal oxides on the exposed portions of thegate lines 121 and the data lines 171 through the contact holes 181-183,is preferably used for the pre-heating process before the deposition ofthe ITO layer, the IZO layer, or the Cr layer.

A TFT array panel for an LCD according to another embodiment of thepresent invention will be described in detail with reference to FIGS. 3and 4.

FIG. 3 is a layout view of an exemplary TFT array panel for an LCDaccording to another embodiment of the present invention, and FIG. 4 isa sectional view of the TFT array panel shown in FIG. 3 taken along thelines IV-VI′, IV′-IV″and IV″-IV″′.

As shown in FIGS. 3 and 4, a layered structure of a TFT array panel ofan LCD according to this embodiment is almost the same as that shown inFIGS. 1 and 2. That is, a plurality of gate lines 121 including aplurality of gate electrodes 123 and a plurality of common electrodeslines 131 including a plurality of common electrodes 133 a and 133 b areformed on a substrate 110, and a gate insulating layer 140, a pluralityof semiconductor stripes 151 including a plurality of projections 154,and a plurality of ohmic contact stripes 161 including a plurality ofprojections 163 and a plurality of ohmic contact islands 165 aresequentially formed thereon. A plurality of data lines 171 including aplurality of source electrodes 173 and a plurality of pixel electrodelines 172 including a plurality of drain electrodes 175 and a pluralityof pixel electrodes 174 a-174 c are formed on the ohmic contacts 161 and165, and a passivation layer 180 is formed thereon. A plurality ofcontact holes 181, 182 and 183 are provided at the passivation layer 180and/or the gate insulating layer 140, and a plurality of redundant datalines 191 and a plurality of contact assistants 95 and 97 are formed onthe passivation layer 180.

Different from the TFT array panel shown in FIGS. 1 and 2, the TFT arraypanel according to this embodiment further extends the extensions 154 ofthe semiconductor stripes 151 and the ohmic contact islands 165 alongthe pixel electrode lines 172 and the pixel electrodes 174 a-174 c.

The semiconductor stripes and islands 151 have almost the same planarshapes as the data lines 171 and the pixel electrode lines 172 as wellas the underlying ohmic contacts 161 and 165, except for portions of theprojections 154 where TFTs are provided. The semiconductor stripes 151include some exposed portions, which are not covered with the data lines171 and the pixel electrode lines 172, such as portions located betweenthe source electrodes 173 and the drain electrodes 175.

Now, a method of manufacturing the TFT array panel shown in FIGS. 3 and4 according to an embodiment of the present invention will be describedin detail with reference to FIGS. 5-9 as well as FIGS. 3 and 4.

FIG. 5-9 are sectional views of a TFT array panel shown in FIGS. 3 and 4in intermediate steps of a manufacturing method thereof according to anembodiment of the present invention.

Referring to FIG. 5, a plurality of gate lines 121 including a pluralityof gate electrodes 123 and a plurality of common electrode lines 131including a plurality of common electrodes 133 a and 133 b are formed ona substrate 110 by photo etching.

As shown in FIG. 6, a gate insulating layer 140, an intrinsic a-Si layer150, and an extrinsic a-Si layer 160 are sequentially deposited by CVDsuch that the layers 140, 150 and 160 bear thickness of about1,500-5,000 Å, about 500-2,000 Å and about 300-600 Å, respectively. Aconductive layer 170 is deposited by sputtering, and a photoresist filmwith the thickness of about 1-2 microns is coated on the conductivelayer 170.

The photoresist film is exposed to light through an exposure mask (notshown), and developed such that the developed photoresist PR has aposition dependent thickness. The photoresist shown in FIG. 6 includes aplurality of first to third portions with decreased thickness. The firstportions are located on wire areas A, the second portions are located onchannel areas C, respectively, and the third portions havingsubstantially zero thickness are located on remaining areas B, whichexpose underlying portions of the conductive layer 170. The thicknessratio of the second portions to the first portions of the photoresist PRis adjusted depending upon the process conditions in the subsequentprocess steps. It is preferable that the thickness of the secondportions is equal to or less than half of the thickness of the firstportions, and in particular, equal to or less than 4,000 Å.

The position-dependent thickness of the photoresist PR is obtained byseveral techniques, for example, by providing translucent areas on theexposure mask as well as transparent areas and light blocking opaqueareas. The translucent areas may have a slit pattern, a lattice pattern,a thin film(s) with intermediate transmittance or intermediatethickness. When using a slit pattern, it is preferable that the width ofthe slits or the distance between the slits is smaller than theresolution of a light exposer used for the photolithography. Anotherexample is to use reflowable photoresist. In detail, once a photoresistpattern made of a reflowable material is formed by using a normalexposure mask only with transparent areas and opaque areas, it issubject to reflow process to flow onto areas without the photoresist,thereby forming thin portions.

The different thickness of the photoresist PR enables to selectivelyetch the underlying layers when using suitable process conditions.Therefore, a plurality of data lines 171 including a plurality of sourceelectrodes 173 and a plurality of pixel electrode lines 172 including aplurality of drain electrodes 175 and a plurality of pixel electrodes174 a-174 c as well as a plurality of ohmic contact stripes 161including a plurality of projections 163, a plurality of ohmic contactislands 165, and a plurality of semiconductor stripes 151 including aplurality of projections 154 are obtained by a series of etching steps.

For descriptive purpose, portions of the conductive layer 170, theextrinsic a-Si layer 160, and the intrinsic a-Si layer 150 on the wireareas A are called first portions, portions of the conductive layer 170,the extrinsic a-Si layer 160, and the intrinsic a-Si layer 150 on thechannel areas C are called second portions, and portions of theconductive layer 170, the extrinsic a-Si layer 160, and the intrinsica-Si layer 150 on the remaining areas B are called third portions.

An exemplary sequence of forming such a structure is as follows:

(1) Removal of third portions of the conductive layer 170, the extrinsica-Si layer 160 and the intrinsic a-Si layer 150 on the wire areas A;

(2) Removal of the second portions of the photoresist PR; (3) Removal ofthe second portions of the conductive layer 170 and the extrinsic a-Silayer 160 on the channel areas C; and

(4) Removal of the first portions of the photoresist PR.

Another exemplary sequence is as follows:

(1) Removal of the third portions of the conductive layer 170;

(2) Removal of the second portions of the photoresist PR;

(3) Removal of the third portions of the extrinsic a-Si layer 160 andthe intrinsic a-Si layer 150;

(4) Removal of the second portions of the conductive layer 170;

(5) Removal of the first portions of the photoresist PR; and

(6) Removal of the second portions of the extrinsic a-Si layer 160.

The first example is described in detail.

As shown in FIG. 7, the exposed third portions of the conductive layer170 on the wire areas B are removed to expose the underlying thirdportions of the extrinsic a-Si layer 160.

FIG. 7 shows portions (referred to as conductors hereinafter) of theconductive layer 170 including the data lines 171 and the pixelelectrode lines 172 connected to each other. The dry etching may etchout the top portions of the photoresist PR. Subsequently, the thirdportions of the extrinsic a-Si layer 160 on the areas B and of theintrinsic a-Si layer 150 are removed.

Referring to FIG. 8, the second portions of the photoresist PR areremoved to expose the second portions of the conductors. The removal ofthe second portions of the photoresist PR are performed eithersimultaneously with or independent from the removal of the thirdportions of the extrinsic a-Si layer 160 and of the intrinsic a-Si layer150. Residue of the second portions of the photoresist PR remained onthe channel areas C is removed by ashing.

The semiconductor stripes 151 are completed in this step, and referencenumeral 164 indicates portions of the extrinsic a-Si layer 160 includingthe ohmic contact stripes and islands 161 and 165 connected to eachother, which are called “extrinsic semiconductor stripes.”

The second portions of the conductors and the extrinsic a-Si stripes 164on the channel areas C as well as the first portion of the photoresistPR are removed.

As shown in FIG. 8, top portions of the projections 154 of the intrinsicsemiconductor stripes 151 on the channel areas C may be removed to causethickness reduction, and the first portions of the photoresist areetched to a predetermined thickness.

In this way, each conductor is divided into a data line 171 and aplurality of pixel electrode lines 175 to be completed, and eachextrinsic semiconductor stripe 164 is divided into an ohmic contactstripe 161 and a plurality of ohmic contact islands 165 to be completed.

Next, a passivation layer 180 is formed by chemical-vapor-depositingsilicon nitride at a temperature in a range of about 250-1500° C., bygrowing low dielectric material such as a-Si:C:O or a-Si:O:F, by CVD ofsilicon nitride, or by coating an organic insulating material such asacryl-based material having a good planarization characteristic.Referring to FIG. 9, the passivation layer 180 as well as the gateinsulating layer 140 is photo-etched to form a plurality of contactholes 181, 182 and 183.

Finally, as shown in FIGS. 3 and 4, a conductor layer such as an IZOlayer with a thickness in a range between about 500 Å and about 1,500 Åis sputtered and photo-etched to form a plurality of redundant datalines 191 and a plurality of contact assistants 95 and 97. The etchingof the IZO layer preferably includes wet etching using a Cr etchant ofHNO₃/(NH₄)₂Ce(NO₃)₆/H₂O, which does not erode Al of the data lines 171and the pixel electrode lines 172.

This embodiment simplifies the manufacturing process by forming the datalines 171 and the pixel electrode lines 172 as well as the ohmiccontacts 161 and 165 and the semiconductor stripes 151 using a singlephotolithography step.

While the present invention has been described in detail with referenceto the preferred embodiments, those skilled in the art will appreciatethat various modifications and substitutions can be made thereto withoutdeparting from the spirit and scope of the present invention as setforth in the appended claims.

1. A thin film transistor array panel comprising: a gate line and a dataline formed on an insulating substrate and intersecting each other; aplurality of common electrodes separated from the gate line and the dataline and making an angle of about 7-23 degrees with the gate line; aplurality of pixel electrodes separated from the gate line, the dataline, and the common electrodes, extending parallel to the commonelectrodes, and alternately arranged with the common electrodes; and athin film transistor connected to the gate line, the data line, and thepixel electrodes. 2-14. (canceled)